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[OS Develop] asynFifo

Description: 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
Platform: | Size: 1024 | Author: leng | Hits:

[VHDL-FPGA-Verilog] fifo1

Description: 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
Platform: | Size: 32768 | Author: 何勇 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO，vhdl实现，希望可以有帮助,大家加油-FIFO VHDL
Platform: | Size: 1024 | Author: Carlin | Hits:

[VHDL-FPGA-Verilog] fifotop

Description: 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
Platform: | Size: 2100224 | Author: 李芳 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用VHDL语言写的FIFO代码，可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
Platform: | Size: 1024 | Author: wd | Hits:

[Software Engineering] CummingsSNUG2002SJ_FIFO2

Description: Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
Platform: | Size: 101376 | Author: sumit | Hits:

[OS Develop] program

Description: 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the first data word written into the RAM is also the first data word retrieved from the RAM. As shown in the Figure 1, the RAM is implemented to operate as a FIFO. The RAM is assumed to have separate data inputs and outputs, an N-bit address bus (ADD) and an active high write enable (WE). The inputs to FIFO/Stack include PUSH, POP, INIT (all active high) in addition to the rising edge triggered CLK input. The FIFO logic will not only supply the address and write enable to the RAM, but will also supply active high flags for FULL, EMPTY, NOPOP, and NOPUSH conditions.
Platform: | Size: 3072 | Author: shao | Hits:

[VHDL-FPGA-Verilog] fifo_vhdl

Description: FIFO的VHDL编程，其中包括FIFO的读，写，满帧，半满帧信号驱动-FIFO of the VHDL programming, including the FIFO' s read, write, full frame, half-full frame signal drive
Platform: | Size: 1024 | Author: 刘石 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo 的vhdl源程序,容量为1024*8的fifo程序代码-fifo the vhdl source code,Capacity of 1024* the fifo code 8
Platform: | Size: 1024 | Author: 谢文华 | Hits:

[VHDL-FPGA-Verilog] fifo.vhd

Description: This a FIFO in VHDL Code-This is a FIFO in VHDL Code
Platform: | Size: 3072 | Author: lagartojj | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[VHDL-FPGA-Verilog] ASYNCFIFO

Description: 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
Platform: | Size: 75776 | Author: Denny | Hits:

[VHDL-FPGA-Verilog] VHDL06

Description: 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
Platform: | Size: 1024 | Author: yanyinhong | Hits:

[VHDL-FPGA-Verilog] 8fifo

Description: 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
Platform: | Size: 3072 | Author: qaz | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 包括用用VHDL语言编写的DDS,FIFO,交通控制灯，数字电压计，信号发生器的源码，希望能帮到大家-Including the use of VHDL language with the DDS, FIFO, traffic control lights, digital voltage, the signal generator of the source, I hope to help you
Platform: | Size: 69632 | Author: link | Hits:

[VHDL-FPGA-Verilog] Asynchronous_FIFO_v6_1

Description: 详细介绍了异步FIFO的设计方法,以及fpga的仿真波形-Described in detail the design of asynchronous FIFO method and the simulation waveform fpga
Platform: | Size: 133120 | Author: wushaojie | Hits:

[VHDL-FPGA-Verilog] VHDLbasicExampleDEVELOPEMENTsoursE

Description: 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用，介绍如下： Chapter3：schematic和vhdl文件夹，分别是数字钟设计的原理图文件和VHDL程序； Chapter4：multiplier文件夹，串并乘法器设计程序（提示：先编译程序包）； Chapter5：sci文件夹，串行通信接口设计程序； Chapter6：watchdog文件夹，看门狗设计程序； Chapter7：taxi文件夹，出租车计价器设计程序； Chapter8：elevator文件夹，高层电梯控制器设计程序； Chapter9：cymometer1和cymometer2文件夹，前者是计数测频设计程序，后者是等精度测频设计程序； Chapter10：digital_lock文件夹，数字密码锁设计程序； Chapter11：I2C文件夹，I2C控制器设计程序； Chapter12：fifo文件夹，异步FIFO设计程序； Chapter13：dds文件夹，数字频率合成设计程序； Chapter14：vLA文件夹，虚拟逻辑分析仪设计程序。 -this book includes 12 detail examples of the source program
Platform: | Size: 139264 | Author: wuyu | Hits:

[Windows Develop] fifo_design

Description: 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
Platform: | Size: 2048 | Author: 孟霑 | Hits:

[Com Port] async_fifo

Description: 异步fifo 源程序代码 欢迎大家学习 用VHDL语言编写-asy fifo
Platform: | Size: 212992 | Author: chenxuhui | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
Platform: | Size: 164864 | Author: Daisy | Hits:
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